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Categories: 3D Nand Toshiba

#Toshiba has just announced that they will begin shipping samples of its 512 Gigabit, three-bits-per-cell, 64-layer #3DNAND ( #BiCS3D ). Mass production is expected to take place during the second half of 2017. Western Digital and Toshiba engineers have used digital stacking for their sixty-four layers in order to achieve a much larger storage density for its NAND in a smaller footprint. This technology also enables 1TB chip solutions. The flash memory stacked cell structure is best for applications that require high capacity and performance. According to Toshiba, “realizes a 65 percent larger capacity per unit chip size than the company’s 48-layer, 256Gb (32 gigabyte) device. This increases memory capacity per silicon wafer and leads to a reduction of cost-per-bit.”

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