Memories Of The Future
At the 2016 #IEEE International Electron Devices ( #IEDM ) Conference in San Francisco several exciting developments were presented that may change the way we keep information in consumer as well as business applications and devices. Although planar (2D) #flashmemory less than 10 nm appears to be off the table, other electronic devices were discussed with 7 nm features (especially FinFETs) and there was even a mention or two of 5 nm features. Let’s look at developments in #NAND as well as emerging memory technologies, such as #MRAM and even #DRAM. In a plenary talk Seok-Hee Lee from SK Hynix spoke about technology scaling challenges and opportunities for memory devices. He said that single-thread CPU performance increases have slowed since 2005 and the cache speeds available for compute cores have been stagnant. As a result the overall delay of computing devices hasn’t improved much recently. He indicated that evolution by itself will not be enough for the future and that memory technology needed to take two revolutionary paths. One of these paths focuses on #highbandwidthmemory and the other on #highcapacitymemory, increasing the complexity of the conventional memory/storage hierarchy.
Below 15 nm 2D flash scaling is about done and we must depend upon #3DNAND for continued #NAND flash advances. 3D NAND needs more efficient cell arrays to reduce the height as cell stacks achieve 100’s of layers. He discussed a concept called Z-scaling to reduce the overall stack height and enabling 356 cell layers. He also discussed the need to include peripheral electronics under the cells to allow more die per wafer. Quad-level cells to increase per cell bit density are another important development. Overall he expected 256 layer NAND flash within 5 years.