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Categories: 3D Nand 3d Xpoint Intel Micron

The non-silicon switching technology in #3DXPoint is priceless. @Intel and @Micron are dropping #3DNAND as a result. But memory will not be the most profitable use of this technology.  After my previous article on Intel ( #INTC ) and Micron ( #MU ), Amazing Powers of Observation, Jim Handy over at Electronic Design penned a similar piece from a very compelling angle. He reaches back to his 2008 prognostication about the scaling of flash memory versus a hypothetical new memory technology. At that time, 3D NAND was not yet a thing so his graph was a projection of planar flash, which was predicted to stop scaling at 10 nanometers. But his logic is still quite valid:  Source: Jim Handy, Objective Analysis January 2008 This article should be read in its entirety. The information presented on this graph dovetails nicely with the point that I was making: flash and DRAM are very near the end of scaling and, at some point very soon, will no longer get cheaper to produce. At this point, the graph should be updated with a big arrow at the flash elbow which indicates that “you are here” and the “new tech” should be renamed to “3D XPoint”. Advertisement  What I neglected to realize is that the timing for this point of inflection is also the same for the silicon transistor which sits at the heart of Moore’s Law. If there’s one thing that I need to summarize as my only real point going all the way back to my first article in 2012, it is that the silicon transistor will reach end of life at 5 nanometers (or 3 nanometers if you fancy TSM (TSM), AMD (AMD), GlobalFoundries, Nvidia (NVDA), or Samsung (OTC:SSNLF) tape measures). While there was some FinFET trickery involved in kicking the silicon can below 28 nanometers, the fact of the matter now is simply that electrons are too big for silicon transistor physics at levels below 5 nanometers. There’s nothing left in this bag. Learn to say “Chalcogenide” The non-silicon “chalcogenide” switching technology in 3D XPoint is currently being sold to any off-the-street yokel who wants to pony-up the cash to buy it (less than $50 to start). The utter lack of celebration surrounding this fact is amazing to me because the technology has been under development for more than 60 years with nary a ribbon-cutting, champagne or even cocktail wieners. Over at his regular site, Handy has dug up the original 47-year-old chalcogenide research which was co-authored by Intel founder Gordon Moore. Here’s a video of related work performed in 1969 at Iowa State (note that the polarity discussion is incorrect) which illustrates the two basic switching mechanisms involved (Ovonic “threshold” switching and “phase change” switching):  Although I didn’t expect it to take this long, I’ve been chasing chalcogenide technology for almost 20 years, and in that time, I’ve acquired what I’d regard as a decent level of related knowledge. Recently, I was able to interview a couple of professional researchers – Guy Wicker and Boil Pashmakov – from Ovonic Cognitive Computer in order to further my understanding of the technology. Wicker and Pashmakov were both involved in the seminal 3D XPoint work at Energy Conversion Devices (“ECD”) which predated Ovonyx (now owned by Micron) and find their names on dozens of related patents – many of which have Intel or Micron assignments on them. Wicker found himself at Intel Santa Clara in the early 2000s but came back to ECD after they built a much more flexible clean room semiconductor lab at ECD in Metro Detroit. When Pashmakov and Ovshinsky patented a method to use chalcogenides to perform in-memory computation, I was enamored as both an investor and a historian – this technology will fundamentally change the world as soon as we traverse the hockey stick bend in Handy’s graph above. Now that Intel and Micron have chalcogenide switching technology in mass production alongside regular silicon, I am finding that the silence is deafening. Regular Joe Six Pack investors will quickly point out that Intel’s Optane really isn’t that good for as much as it costs.

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