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Categories: 3d Xpoint Intel Micron

Summary @Intel and @Micron have confirmed that #IMFT is now dedicated to #3DXPoint. In 2009, Intel announced that it would replace flash with XPoint. Investors remain oblivious to this opportunity.  On January 5th, I penned an article that quickly forced Intel (NASDAQ:INTC) and Micron (NASDAQ:MU) to explain for investors that their IMFT relationship is moving on from 3D NAND technology in order to shift focus exclusively on 3D XPoint. Not that this information wasn’t sitting in broad daylight by way of Micron’s most recent 10-Q, I just can’t imagine that they expected anyone to actually read it. In the first quarter of 2018, IMFT discontinued production of NAND and continues to ramp production of 3D XPoint products. This is how I’ve made most of my “discoveries” over the past couple of decades – through my amazing powers of observation. The article before you now is a summary of these observations. The first comes from October 28th, 2009: Intel Corporation and Numonyx B.V. today announced a key breakthrough in the research of phase change memory (“PCM”), a new non-volatile memory technology that combines many of the benefits of today’s various memory types. For the first time, researchers have demonstrated a 64Mb test chip that enables the ability to stack, or place, multiple layers of PCM arrays within a single die. These findings pave the way for building memory devices with greater capacity, lower power consumption and optimal space savings for random access non-volatile memory and storage applications. […] Advertisement  “The results are extremely promising,” said Greg Atwood, senior technology fellow at Numonyx. “The results show the potential for higher density, scalable arrays and NAND-like usage models for PCM products in the future. This is important as traditional flash memory technologies face certain physical limits and reliability issues, yet demand for memory continues to rise in everything from mobile phones to data centers.” Just shortly after this announcement, Micron purchased Numonyx on February 9th, 2010. Micron’s stock plummeted as a result. This was an easy call for investors because Numonyx largely produced NOR flash, a technology which was on the decline. It has largely been displaced by a combination of NAND and DRAM at this point. Behind the scenes, Micron did get something of potentially tremendous value: the right to call Intel’s ownership in IMFT. Again, from Micron’s December 10-Q: At any time through December 2018, Intel can put to us, and from January 2019 through December 2021, we can call from Intel, Intel’s interest in IMFT, in either case, for approximately the net book value of Intel’s noncontrolling interest balance at the time of the closing. If Intel exercises its put right, we can elect to set the closing date of the transaction any time between six months and two years following such election by Intel and can elect to receive financing of the purchase price from Intel for one to two years from the closing date. If we exercise our call right, Intel can elect to set the closing date of the transaction to be any time between six months and one year following such election. Following the closing of either the put or the call, we will continue to supply to Intel for a period of one year, at Intel’s choice, between 50% and 100% of Intel’s immediately preceding six-month period pre-closing volumes of IMFT products for the first six-month period following the closing and, at Intel’s choice, between 0% and 100% of Intel’s first six-month period following the closing volumes of IMFT products for the second six-month period following the closing, at a margin that varies depending on whether the put or call was exercised. And That is How I Know Storing data in the form of electrons is idiocy at today’s fabrication scales (that goes for both NAND and DRAM). This fact isn’t discussed publicly by the industry but its poker face isn’t that good. About a year ago, Samsung (OTC:SSNLF) shipped what it called “10 nanometer class” DRAM. After it was recently torn down by TechInsights, we can now see that this classification was smothered in marketing syrup: the chip is fabbed at 18 nanometers. It spent all of that money to go from 20nm to 18, so calling it “10 nanometer class” is nothing but spin. I expect the second iteration of “10 nanometer class” DRAM to be 17 or maybe 16nm, and I also expect it to be the last – it will die on the vine to be replaced by new technologies at that point. Industry insiders do not expect that there will ever be actual 10 nanometer DRAMs. The same goes for flash memory. In the following video, Intel’s Rick Coulson outlines just how error-prone NAND is now that it is finished scaling horizontally:  It is to be appreciated that before 3D NAND was a thing, Intel opted out of IMFT’s 16nm NAND because the error rates were too high for its use cases – it stayed with the larger, more reliable 20nm product. A sobering realization from Samsung at last August’s Flash Memory Summit is that it’s reached what appears to be a very substantial limit in scaling NAND vertically. From its 96-layer 3D NAND presentation: Beyond the fifth generation, Samsung says they may start using techniques like string stacking, putting the peripheral logic under the memory array, or shrinking the horizontal dimensions of their flash. String stacking is more or less inevitable if the layer count is to continue increasing, but it is not clear exactly when that transition will be worthwhile. At the moment, Samsung estimates string stacking would increase production costs by about 15% due to the extra process steps involved, and aligning a second stack of 3D NAND layers will present serious yield challenges. […] Shrinking the horizontal dimensions of their NAND flash memory cells also offers a way to increase density and improve price per GB, but that path leads to the same endurance and reliability problems that eventually made planar NAND a dead end technology. This discussion also included significant information on the tremendous fab processing time that is required to bake a 3D NAND layer cake of any substantial capacity. Attendees walked away knowing that we’re very near to the end of the easy money. Buried in the Intel and Micron IMFT update is the admission that their 3rd-gen 3D NAND (likely 96-layer as well) will be the last of the jointly produced 3D NAND. The doom and gloom prognosticators, failing to have read the information put forth by Intel in 2009 with countless reinforcement in the following years, all see this as a bad thing. They are wrong – it is clear to me that we’ve reached the turning point: flash is now end-of-life and Intel and Micron are transitioning into 3D XPoint as they’ve planned and disclosed for over a decade now. That is to say that the 3rd-gen 3D NAND from Intel and Micron is the last-gen from the couple. Don’t get me wrong: 3D NAND won’t go away for a long while (we’ll need a cheap technology to backfill low-end and mid-range products). It will, however, stop scaling in the next couple of years. Although version 1.0 of 3D XPoint was ho-hum, version 1.1 is now out and is finally beginning to impress. Investors need to realize the following: Existing 3D XPoint has only stacked to a height of two layers but they can easily see that double. Existing 3D XPoint has suboptimal density in order to prevent thermal cross-talk from disturbing memory cells which are adjacent to high-activity cells. This problem has been solved. Existing 3D XPoint stores only a single bit per cell (“SLC”) but has the capability to store up to four (“QLC”) or more. I expect to see 3D XPoint v2.0 released in a manner which addresses the first two items on this list: more layers with better density per layer. The existing two-layer 128Gbit SLC chip will likely increase to 128Gbit per layer and then stack another two layers for a total of four, resulting in a total of 512Gbit – that’s 64 gigabytes of storage-class memory on a single chip. They might play with storing multiple bits per cell just for the sake of stealing some thunder in the form of a QLC version of 3D XPoint v2.0 which would be 2Tbit, double the size of Samsung’s much-touted 96-layer 3D NAND. However, storing multiple bits per cell in 3D XPoint would come at a tremendous impact to performance. Depending on required on-chip overhead, this might be a trivial task, leaving the trade-off to be selectable by the end-user. Conclusion We know that Intel just bet the farm on IMFT and 3D XPoint because it did not exercise its right to put its share to Micron, but instead invested heavily. Additionally, they confirmed that their IMFT “joint venture fab in Lehi, Utah, is now entirely focused on 3D XPoint memory production.” More interesting is Micron’s call option on IMFT. We’re less than a year away from that now, so I surmise that the months to come will be very interesting for Micron’s shareholders.

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